As the number of components present in an integrated circuit increases, attempts are made by the skilled artisan to decrease the size of individual components to prevent the individual integrated circuit chips from becoming prohibitively large. With respect to a common component, such as field effect transistors, for example, these attempts might reduce the sizes of the source/drain regions or the channel length, i.e., the distance between the source and drain regions, thereby permitting smaller transistors to be fabricated. Additional reduction in chip size may be obtained by use of more compact electrical connections to the transistor elements. For example, the gate structure might be contacted near the source/drain regions rather than on a runner on the field oxide which electrically isolates individual devices.
See, for example, U. S. Pat. No. 4,822,754 issued on Apr. 18, 1989 to Lynch et al. and also U. S. Pat. No. 4,844,776 on Jul. 4, 1989 to Lee et al. for descriptions of approaches which permit reduction of device and feature sizes.
In addition to reducing feature size, i.e., simple scaling of device dimensions, structural changes in the devices or integrated circuit components are desirable for many reasons. For example, the source/drain regions are typically formed by ion implantation or impurity diffusion into the silicon substrate. The term substrate is used to mean a material which lies underneath and supports another material. The term thus includes an epitaxial layer, if present. Some of the problems associated with the implanted source/drain configuration can, at least in theory, be eliminated or alleviated by what is termed a raised source/drain region.